

#ifndef __STC12C5410AD_H__
#define __STC12C5410AD_H__

#include "compiler.h"

/* After is STC additional SFR or change */
/* sfr  AUXR  = 0x8e; */
/* sfr  IPH   = 0xb7; */

/* Watchdog Timer Register */
SFR(WDT_CONTR,0xe1);

/* ISP_IAP_EEPROM Register */
SFR(ISP_DATA,0xe2);
SFR(ISP_ADDRH,0xe3);
SFR(ISP_ADDRL,0xe4);
SFR(ISP_CMD,0xe5);
SFR(ISP_TRIG,0xe6);
SFR(ISP_CONTR,0xe7);

/* System Clock Divider */
SFR(CLK_DIV,0xc7);

/* I_O Port Mode Set Register */
SFR(P0M0,0x93);
SFR(P0M1,0x94);
SFR(P1M0,0x91);
SFR(P1M1,0x92);
SFR(P2M0,0x95);
SFR(P2M1,0x96);
SFR(P3M0,0xb1);
SFR(P3M1,0xb2);

/* SPI Register */
SFR(SPSTAT,0x84);
SFR(SPCTL,0x85);
SFR(SPDAT,0x86);

/* ADC Register */
SFR(ADC_CONTR,0xc5);
SFR(ADC_DATA,0xc6);
SFR(ADC_LOW2,0xbe);

/* PCA SFR */
SFR(CCON,0xD8);
SFR(CMOD,0xD9);
SFR(CCAPM0,0xDA);
SFR(CCAPM1,0xDB);
SFR(CCAPM2,0xDC);
SFR(CCAPM3,0xDD);
SFR(CCAPM4,0xDE);
SFR(CCAPM5,0xDF);

SFR(CL,0xE9);
SFR(CCAP0L,0xEA);
SFR(CCAP1L,0xEB);
SFR(CCAP2L,0xEC);
SFR(CCAP3L,0xED);
SFR(CCAP4L,0xEE);
SFR(CCAP5L,0xEF);

SFR(CH,0xF9);
SFR(CCAP0H,0xFA);
SFR(CCAP1H,0xFB);
SFR(CCAP2H,0xFC);
SFR(CCAP3H,0xFD);
SFR(CCAP4H,0xFE);
SFR(CCAP5H,0xFF);

SFR(PCA_PWM0,0xF2);
SFR(PCA_PWM1,0xF3);
SFR(PCA_PWM2,0xF4);
SFR(PCA_PWM3,0xF5);
SFR(PCA_PWM4,0xF6);
SFR(PCA_PWM5,0xF7);

/*  CCON  */
SBIT(CF,0xD8,7);
SBIT(CR,0xD8,6);
SBIT(CCF5,0xD8,5);
SBIT(CCF4,0xD8,4);
SBIT(CCF3,0xD8,3);
SBIT(CCF2,0xD8,2);
SBIT(CCF1,0xD8,1);
SBIT(CCF0,0xD8,0);


/* Above is STC additional SFR or change */

/*--------------------------------------------------------------------------
REG51F.H

Header file for 8xC31/51, 80C51Fx, 80C51Rx+
Copyright (c) 1988-1999 Keil Elektronik GmbH and Keil Software, Inc.
All rights reserved.

Modification according to DataSheet from April 1999
 - SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives
--------------------------------------------------------------------------*/

/*  BYTE Registers  */
SFR(P0,0x80);
SFR(P1,0x90);
SFR(P2,0xA0);
SFR(P3,0xB0);
SFR(PSW,0xD0);
SFR(ACC,0xE0);
SFR(B,0xF0);
SFR(SP,0x81);
SFR(DPL,0x82);
SFR(DPH,0x83);
SFR(PCON,0x87);
SFR(TCON,0x88);
SFR(TMOD,0x89);
SFR(TL0,0x8A);
SFR(TL1,0x8B);
SFR(TH0,0x8C);
SFR(TH1,0x8D);
SFR(IE,0xA8);
SFR(IP,0xB8);
SFR(SCON,0x98);
SFR(SBUF,0x99);

/*  80C51Fx/Rx Extensions  */
SFR(AUXR,0x8E);
/* sfr AUXR1  = 0xA2; */
SFR(SADDR,0xA9);
SFR(IPH,0xB7);
SFR(SADEN,0xB9);
//stc12c5410ad have no T2 timer
SFR(T2CON,0xC8);
SFR(T2MOD,0xC9);
SFR(RCAP2L,0xCA);
SFR(RCAP2H,0xCB);
SFR(TL2,0xCC);
SFR(TH2,0xCD);


/*  BIT Registers  */
/*  PSW   */
SBIT(CY,0xD0,7);
SBIT(AC,0xD0,6);
SBIT(F0,0xD0,5);
SBIT(RS1,0xD0,4);
SBIT(RS0,0xD0,3);
SBIT(OV,0xD0,2);
SBIT(P,0xD0,0);

/*  TCON  */
SBIT(TF1,0x88,7);
SBIT(TR1,0x88,6);
SBIT(TF0,0x88,5);
SBIT(TR0,0x88,4);
SBIT(IE1,0x88,3);
SBIT(IT1,0x88,2);
SBIT(IE0,0x88,1);
SBIT(IT0,0x88,0);

/*  P3  */
SBIT(RD,0xB0,7);
SBIT(WR,0xB0,6);
SBIT(T1,0xB0,5);
SBIT(T0,0xB0,4);
SBIT(INT1,0xB0,3);
SBIT(INT0,0xB0,2);
SBIT(TXD,0xB0,1);
SBIT(RXD,0xB0,0);

/*  SCON  */
SBIT(SM0,0x98,7); // alternatively "FE"
SBIT(FE,0x98,7);
SBIT(SM1,0x98,6);
SBIT(SM2,0x98,5);
SBIT(REN,0x98,4);
SBIT(TB8,0x98,3);
SBIT(RB8,0x98,2);
SBIT(TI,0x98,1);
SBIT(RI,0x98,0);
             
//no T2
SBIT(T2EX,0x90,1);
SBIT(T2,0x90,0);

/*  T2CON  */
SBIT(TF2,0xC8,7);
SBIT(EXF2,0xC8,6);
SBIT(RCLK,0xC8,5);
SBIT(TCLK,0xC8,4);
SBIT(EXEN2,0xC8,3);
SBIT(TR2,0xC8,2);
SBIT(C_T2,0xC8,1);
SBIT(CP_RL2,0xC8,0);

/* PCA Pin */

SBIT(CEX3,0xA0,4);
SBIT(CEX2,0xA0,0);
SBIT(CEX1,0xB0,5);
SBIT(CEX0,0xB0,7);
SBIT(ECI,0xB0,4);

/*  IE   */
SBIT(EA,0xA8,7);
SBIT(EPCA_LVD,0xA8,6);
SBIT(EADC_SPI,0xA8,5);
SBIT(ES,0xA8,4);
SBIT(ET1,0xA8,3);
SBIT(EX1,0xA8,2);
SBIT(ET0,0xA8,1);
SBIT(EX0,0xA8,0);

/*  IP   */ 
SBIT(PPCA_LVD,0xB8,6);
SBIT(PADC_SPI,0xB8,5);
SBIT(PS,0xB8,4);
SBIT(PT1,0xB8,3);
SBIT(PX1,0xB8,2);
SBIT(PT0,0xB8,1);
SBIT(PX0,0xB8,0);

/*------------------------------------------------
Interrupt Vectors:
Interrupt Address = (Number * 8) + 3
------------------------------------------------*/
#define IE0_VECTOR	0  /* 0x03 External interrupt 0 */
#define TF0_VECTOR	1  /* 0x0B Timer 0 */
#define IE1_VECTOR	2  /* 0x13 External interrupt 1 */
#define TF1_VECTOR	3  /* 0x1B Timer 1 */
#define SIO_VECTOR	4  /* 0x23 Serial port */
#define ADCSPI_VECTOR 5 /*0x2B ADC_FLAG + SPIF*/
#define PCALVD_VECTOR 6 /*0x33 CF + CCF0 + CCF1 + CCF2 + CCF3 + LVDF*/

#endif//__STC12C5410AD_H__
